# Nanostack

> **TL;DR.** Nanostack is IBM's three-dimensional transistor architecture that stacks complementary NMOS and PFET nanosheets vertically in staggered layers, exploiting the z-axis to break through the 1nm barrier and enter what IBM calls the "angstrom era" of chip scaling.

- **Category:** Hardware / Semiconductor / Transistor Architecture
- **Stage:** nascent
- **Age:** 1 days
- **Origin date:** 2026-06-25
- **First detected:** 2026-06-26
- **Canonical URL:** https://earlyterms.com/term/nanostack
- **Sources:** 8 primary URLs

## Definition

Nanostack is IBM's three-dimensional transistor architecture that stacks complementary NMOS and PFET nanosheets vertically in staggered layers, exploiting the z-axis to break through the 1nm barrier and enter what IBM calls the "angstrom era" of chip scaling.

Unveiled June 25, 2026 at the [VLSI 2026](https://newsroom.ibm.com/2026-06-25-ibm-debuts-worlds-first-sub-1-nanometer-chip-technology) symposium, the prototype packs nearly 100 billion transistors on a fingernail-sized die at a 0.7nm (7 angstrom) node — roughly double the density of IBM's 2021 2nm chip — with gains of 50% higher performance and 70% lower power versus that prior generation.

## Analogy

Think of it as turning a single-story transistor floor plan into a staggered two-story building on the same plot.

## Why it's emerging now

On June 25, 2026, IBM presented validated hardware at VLSI 2026 achieving 666 million transistors per mm² — more than 2.8x TSMC N2 — using a staggered 3D CFET design that exploits the z-axis instead of shrinking horizontally. The milestone pushes chips below 1nm for the first time, a barrier physicists had flagged as the end of conventional scaling.

## Related terms

- *parent:* GAAFET
- *related:* CFET
- *parent:* nanosheet transistor
- *related:* FinFET
- *related:* angstrom era
- *related:* 3D sequential integration
- *related:* Moore's Law
- *competitor:* TSMC N2
- *competitor:* Intel 18A
- *related:* ai-capex
- *related:* dgx-spark

## Sources

1. [IBM Newsroom — Debuts World's First Sub-1 Nanometer Chip Technology (Jun 25, 2026)](https://newsroom.ibm.com/2026-06-25-ibm-debuts-worlds-first-sub-1-nanometer-chip-technology)
2. [IBM Research — What is IBM's nanostack chip architecture?](https://research.ibm.com/blog/what-is-a-nanostack)
3. [IBM Research — Sub-1nm node chips explainer](https://research.ibm.com/blog/sub-1nm-node-chips)
4. [MIT Technology Review — IBM unveils sub-1nm chip (Jun 25, 2026)](https://www.technologyreview.com/2026/06/25/1139696/ibm-unveils-sub1nm-chip/)
5. [More Than Moore — IBM's 0.7nm Process Node, Nanostack deep-dive (Jun 25, 2026)](https://morethanmoore.substack.com/p/ibms-announces-07nm-process-node)
6. [Digit.in — NanoStack explained: Did IBM really build a 0.7nm chip?](https://www.digit.in/features/general/nanostack-explained-did-ibm-really-build-a-07nm-chip.html)
7. [ServeTheHome — IBM Outlines Sub-1nm Nanostack Transistor Technology](https://www.servethehome.com/ibm-outlines-sub-1nm-nanostack-transistor-technology/)
8. [Let's Data Science — IBM debuts 0.7nm Nanostack with nearly 100B transistors](https://letsdatascience.com/news/ibm-debuts-07nm-nanostack-with-nearly-100b-transistors-f05b42f2)

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